A conventional CMOS output driver stage for a memory chip package is shown in FIG. 1. The driver includes a p-channel transistor 10 and an n-channel transistor 12 connected in series. The sources of transistors 10 and 12 are connected to internal power lines 14 and 16 on the chip. Line 14 is a V.sub.cc bus, while the other line 16 is a ground bus. The drains of transistors 10 and 12 are connected together and to a common output line 18 on the chip. Each gate 20 and 22 of transistors 10 and 12 is driven by gate turn-on and turn-off drivers 24, which are controlled by gate driver logic 26. When p-channel transistor 10 is on, n-channel transistor 12 is off, and vice-versa.
A conventional transistor construction for n-and p-channel transistors 10 and 12 is shown in FIG. 2. Here, n-channel transistor 12 has a plurality of spaced apart parallel diffusion zones defined in an area 28 of a semiconductor substrate and conductive lines which contact the diffusion zones to form alternating source elements S and drain elements D. The source elements S are electrically connected in parallel to ground bus 16, and the drain elements D are likewise electrically connected in parallel to output line 18 to form interlaced comb-like source and drain electrodes. Polysilicon gate electrode elements G pass between source and drain elements S and D and are electrically connected in parallel to gate line 22 in the most direct manner possible to form a comb-like gate electrode. Each of the polysilicon gate electrode elements G are usually less than 100 microns in length to avoid RC delay in the gate.
A problem with this conventional design is the presence of unwanted and sometimes high voltage noise spikes on the V.sub.cc and ground lines 14 and 16 of the chip whenever the output driver stage switches to a new state. These voltage spikes become more severe as the switching time is reduced in high-speed memory chips, and their presence is especially evident in byte-wide memory designs, as when all eight outputs in an 8-bit memory switch from all zero's to all one's, or vice versa. Excessive output noise will cause a memory chip to produce erroneous data.
Referring again to FIG. 1, voltage spikes on the power lines 14 and 16 on a chip are mainly due to parasitic inductance L in the IC package leads and bond wires 30 and 31. The voltage V developed across the inductance L is given by ##EQU1## where I is the current through the output drivers and dI/dt is the change in current per unit time, also known as the output slew rate.
Noise can be reduced by reducing the output slew rate during switching. One commonly used method to reduce output slew rate is to simply reduce the size of the output transistor. This technique cannot be used where large output transistors are needed to supply large amounts of output current such as in high speed circuits. In a paper by Will C. H. Gubbels, et al., "A 40 ns/100 pF Low-Power Full-CMOS 256K (32K.times.8) SRAM", IEEE Journal of Solid-State Circuits, October 1987, pp. 741-747, constant dI/dt behavior is obtained by controlling the gate drive to the output transistor with a special drive circuit. Another approach would be to carefully scale the gate driver circuit, but this method is sensitive to processing and temperature variations. In a paper by George Canepa et al., "A 90 ns 4Mb CMOS EPROM", 1988 IEEE International Solid-State Circuits Conference, February 1988, pp. 120-121, the outputs are switched in succession rather than all at once to reduce the effective dI/dt seen at the inductive power busses.
An object of the present invention is to provide output driver circuit elements that reduce noise on the chip busses during output switching.